The present invention relates to data processing systems and, more particularly, to memories used in data processing systems.
Over the past several years, there has been a significant increase in the capability of data processing systems. This increase is due, to a large extent, to the availability of high density memories, that is, memories capable of storing large quantities of data in a relatively small amount of physical space.
Two types of errors are known to commonly affect the reliability of high density memories. One type of error is termed a "hard error". A hard error is attributable to a physical defect in the memory and can be permanently corrected only by removing and replacing the defective memory. Hard errors can be reduced and even substantially eliminated by stringent quality control measures during the manufacture of memory devices.
A second, more troublesome type of error is a "soft error". Soft errors are not due to any permanent physical defect and, consequently, cannot be eliminated by quality control measures. They have been attributed to any one of a number of causes, with the most recent studies indicating alpha particle radiation as the leading cause. Soft errors are completely unpredictable in occurrence, but they have been found to be more common in high density, dynamic memories, where an extremely small amount of charge represents the data stored in each cell of such memories.
There have been proposals to reduce soft errors in high density memories. One such proposal has been to provide protective coatings to certain parts of the memories or to change some of the materials used in packaging the memories. However, this approach substantially increases manufacturing costs.
In some instances, manufacturers of semiconductor chips have completely ignored the problems caused by soft errors, and have relied on the purchaser or user of the memories to design their own mechanisms for overcoming the problem. For example, the user can provide error correction code (ECC) circuitry on data buses or the like, so that as data is transferred from a memory to some other part or subsystem of a data processing system, a check may be made for any errors in the data bits, and a correction made if an error is detected. The provision of error correction circuitry external to the memory, however, increases the cost of manufacturing data processing systems. Furthermore, such circuitry relies on the external accessing of data before a correction is made. If a data word is accessed infrequently, it may be subject to one or more soft errors before it is checked for errors. When more than one soft error has occurred in the same data word, correction of such errors is difficult with current bit correction techniques.
Insofar as is known, there have been no proposals in the past to incorporate ECC circuitry within a memory system that operates periodically to reduce soft errors. U.S. Pat. No. 3,989,894, issued to Pierre Charransol, does show an error detection and correction circuit for use with a circulating or shift register-type memory. The error detection and correction circuit periodically compares bits in the circulating memory with the same or derived bits stored in an auxiliary memory. The comparison is made, however, in order to check for and correct a lack of synchronization, rather than check for and correct soft errors.